1. Field of Invention
The present invention relates generally to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of computing delays for cells in ASICs.
2. Description of Related Art
An integrated circuit chip (hereafter referred to as an “integrated circuit” (IC), “ASIC”, or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected. A netlist is a list of nets for a chip; more generally a netlist is a description of the logic cells and their connections.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Currently, the minimum geometric feature size of a component is on the order of less than 45 nm, at the process node of 45 nm. Feature sizes will be reduced even further as technology progresses. This small feature size allows fabrication of many transistors on a chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements on them.
ASIC design flow is a combination of logical design and physical design, and includes a variety of steps, which include and are not limited to design entry, logic synthesis, system partitioning, floorplanning, placement, routing, and simulation, with constant feedback in these processes. The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality. Libraries characterize different devices and components used in the ASIC design flow, with the components simulated according to the program SPICE (Simulation Program with Integrated Circuit Emphasis), a general purpose analog electronic circuit simulator used in IC design to check the integrity of circuit designs and to predict circuit behavior. Libraries exist to characterize semiconductor devices at various parameters including process node, voltage, temperature and the like.
ASIC designers further need a timing model for each cell used in an ASIC to determine the performance of the ASIC, including timing closure. Timing closure includes the ability of an ASIC cell or block to transmit and/or process a signal within specified time parameters in a specification. Various types of delay exist in an IC including but not limited to pin-to-pin delay between input and output pins of a logic cell, pin delay, and net or wire delay. Typically it is too time-consuming to build every cell in silicon and measure actual cell delays, instead, designers simulate the delay in a cell, a process called characterization.
Due to the large number of components and the exacting details required by the fabrication process, logical and physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
In an ASIC, the layout design process involves several steps. The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
Regarding partitioning, a chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore, the layout is normally partitioned by grouping the components into blocks such as sub-circuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks.
The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 or more blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks.
Regarding floor planning and placement, this step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor planning is a critical step as it sets up the ground work for a good layout. During placement, the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
Regarding routing, the objective of the routing phase is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel. Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space.
Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes the exact channel routing of wires.
In order for circuit designers to calculate the performance of ASICs, the designers need to compute the delays of the cells in the ASICs. Two types of delays are considered. The first type of delay is the propagation delay of a cell. A propagation delay of a cell is defined as the time duration a signal takes to travel from the input to the output of a cell. The measurement point at the input is called the switching threshold. A propagation delay of a cell is defined for every input to output pin combination of a cell under both the rising and falling input conditions. The propagation delay is also affected by a given process (P), voltage (V) and temperature (T).
The second type of delay is the setup/hold time delay which is an input constraint for sequential cells. The setup time is defined as the time duration a data signal is required to be available at the input of a cell before the clock signal transition, and the hold time is defined as the time duration a data signal is required to be stable after the clock signal transition. For the purpose of explanation, both propagation delay and setup/hold time, can be referred as delay.
As the semiconductor industry advances to a smaller process node, especially 90 nm and below, there is a need for more sign-off corners in STA (statistical timing analysis). Corners is a term of art and may be thought of as extremes in process (P), voltage (V) and temperature (T) at which a circuit design has to achieve timing closure for a particular time requirement and operate according to specification; a sign-off is a guarantee that the circuit can perform at a particular corner combination. A sign-off corner is thus a sort of factor of safety that a chip or ASIC can operate satisfactorily.
However, more sign-off corners have a drawback: more library generation at each specific corner, which results in tremendous characterization time. By way of example, a cell library may have as parameters three external variables P (process, i.e., N-doped/P-doped parameters at a particular feature size), T (temperature) and V (voltage), with each of these variables being split into nominal (NOM), best case (BC) or worse case (WC), to factor in a factor of safety, with temperature varying from a low of say −40 C to a high of 125 C, and voltage varying +/−10% from VDD. If one were to generate all corner libraries for all the different PVT combinations to satisfy all possible customers, there might be over twenty combinations, such as: BC PVT (best case for P, V and T); BC PV+WC T (best case for P, V and worse case for T); BC P+WC VT (best case for P, worse case for V and T); WC PVT (worse case P, V and T); WC PV+BC T (worse case P, V and best case T); and WC P+BC VT (worse case P and best case V, T).
A derating equation is used to rapidly compute the delay in an ASIC cell; otherwise calculating delay would take longer. The derating equation(s) used by the assignee of the present invention to compute the delay of a cell for a given P, V and T of a cell is given by U.S. Pat. No. 6,820,048 (the '048 patent), issued to Bhutani et al. (Nov. 16, 2004), and U.S. Pat. No. 6,484,297 (the '297 patent), issued to Dixit et al. (Nov. 19, 2002), all incorporated herein by reference in their entireties.
Further, the following equations are used for deratings, which are derivatives of the equations in the '048 and '297 patents:DelayCorner=Delay0+(K1*V*Fanout+K2*V*Ramptime+K3V*Fanout*Ramptime+K4V)*DeltaV  Equation 1DelayCorner=Delay0+(K1*T*Fanout+K2*T*Ramptime+K3T*Fanout*Ramptime+K4T)*DeltaV  Equation 2
where: Delay0 is a prior delay; K1, K2 are derating equation factors as described in the '297 and '048 patents; T, V are temperature and voltage; and Fanout, Ramptime are the fan-out and ramptime of the ASIC components under investigation.
The above equation is also equally good for other timing considerations like setup/hold. When calculating delay, a cell delay library is used, with the cell delay library including a table for each timing arc in the library, indexed by input ramptime and output fanout load. The base corner library is then characterized for delay values, at four points. The delay number of these four points plus equations (1) and (2) is used to calculate the four K factors. Once the K factors are obtained, another library can be generated from this base library, using equations (1) and (2). However, since equations (1) and (2) are linear with respect to V and T, and vary as the square with respect to Fanout and Ramptime, the delay vs. PVT is highly nonlinear, and this causes a decrease in accuracy when a corner library is far away from the base corner.
What is lacking in the prior art is a method and apparatus for an improved process to calculate delay and to generate libraries for ASIC components during STA, such as taught in the present invention.